Lab Dashboard
PHASE 6 · 26 ENGINES · ADVANCED ANALYSIS · RF · VISUALIZATION
Circuit Simulator — MNA + Semiconductors
SPICE · DC/AC/Transient · Diode · BJT · MOSFET · Op-Amp
Full MNA solver with semiconductor models. DC operating point, AC sweep, transient analysis with Euler integration. Probe nodes, parametric sweep, save/load circuits.
SIG//BENCH — Signal Workbench
Scope · Wavegen · Logic · Spectrum · Network · Hardware Bridge · Calibration
9-instrument virtual bench with WebSerial hardware bridge. 2-ch scope with FFT, arbitrary wavegen, logic analyzer, network/impedance analyzers. CSV/VCD export. Probe compensation & calibration.
Op-Amp Laboratory
7 Topologies · Gain · Bandwidth · CMRR · Slew Rate
Interactive op-amp design: inverting, non-inverting, differential, integrator, differentiator, summing, comparator. Real gain/bandwidth/phase calculations with frequency response.
Transistor Laboratory
BJT Biasing · MOSFET Switching · Load Lines · Classes
BJT bias point calculator with load line visualization, DC/AC operating point. MOSFET I-V curves, switching analysis, and amplifier class comparison (A/B/AB).
ADC / DAC Deep Dive
Sampling · Nyquist · Quantization · Aliasing · Reconstruction
Interactive sampling theory visualization. Watch aliasing in real-time. Adjust sample rate, resolution, see quantization noise and SNR. Reconstruction filter design.
Power Electronics
Buck · Boost · Buck-Boost · LDO · Efficiency · Thermal
Design switching regulators with real inductor/capacitor sizing. Efficiency curves, ripple calculation, load transient response. LDO dropout and thermal modeling.
PCB Layout Fundamentals
Schematic → Footprint → Routing → DRC → Gerber
Place components on a virtual PCB, route traces with DRC checking, define board outline, and understand layer stackup. Export to Gerber preview.
PAPER//DESIGN
Block Diagram → VHDL · XDC · TCL · Auto-Wire · Resource Est.
Visual FPGA paper design tool. Drag-and-drop peripheral blocks (CLK, UART, SPI, I2C, GPIO, PWM, DDS), auto-wire connections, and generate synthesizable VHDL entity/architecture with XDC constraints and Vivado TCL scripts.
FPGA IDE + Logic Evaluator
VHDL · Real Gate Simulation · Synthesis
VHDL editor with real logic evaluation and Zynq-7020 resource estimation.
RPi Terminal Emulator
Linux · GPIO · I2C · SPI · Python
Full terminal with virtual filesystem, GPIO control, I2C bus scan, Python script execution.
Structured Learning Paths
4 Tracks · Theory → Lab → Quiz · Prerequisites · Skill Tree
Guided curriculum from fundamentals to advanced. Each module has theory content, interactive diagrams, hands-on lab exercises, and knowledge checks. Track your progress across the full skill tree.
Challenge Mode
Build-to-Spec · Fault Diagnosis · Quiz Engine · Auto-Grade
Test your skills: design circuits to meet specifications, diagnose faults in broken circuits, answer timed quizzes. Auto-grading with detailed feedback and scoring.
Lab Notebook
Document · Markdown · Export PDF · Lab Reports
Record observations, capture circuit screenshots, document procedures and results. Export polished lab reports as Markdown. Timestamped entries with tagging.
Monte Carlo Analysis
Tolerance Sweep · Temperature · Noise Floor · Parametric Optimizer
Statistical circuit analysis: run 1000+ trials with component tolerances, temperature coefficients, and noise models. Histogram output with yield prediction. Auto-optimizer tunes component values to meet design specs.
RF & Signal Integrity
Smith Chart · Eye Diagram · Filter Design · Transmission Lines
Impedance matching with interactive Smith Chart, serial link eye diagram generator, Butterworth/Chebyshev/Bessel filter wizard, and microstrip/stripline calculator.
Visualization Engine
Bode Plots · Nyquist · Polar · Waveform Math · Histograms
Professional-grade interactive plots: Bode with cursor readouts, Nyquist stability diagrams, polar patterns, waveform math (multiply, integrate, derivative, envelope), and statistical histogram views.
Circuit Simulator
MNA · DC/AC/TRANSIENT · SEMICONDUCTORS · PROBE · SAVE/LOAD
SIG//BENCH
VIRTUAL INSTRUMENT BENCH · 9 INSTRUMENTS · HARDWARE BRIDGE
2.0V
1.5V
CH1 Vpp
—
CH1 Freq
—
CH1 Vrms
—
CH2 Vpp
—
CH2 Freq
—
Phase Δ
—
W1 OUTPUT
Hz
Vpp
V
W2 OUTPUT
Hz
Vpp
V
ARBITRARY WAVEFORM EDITOR
Draw custom waveform by clicking/dragging on the canvas
|Z| @ 1kHz
—
Phase @ 1kHz
—
Rs (Series R)
—
Cs/Ls
—
Q Factor
—
D Factor
—
V+ POSITIVE SUPPLY
0.000
VOLTS
0V5V
V- NEGATIVE SUPPLY
0.000
VOLTS
-5V0V
CONNECTION STATUS
No Device
Click 'Connect Device' to begin
Port—
Baud Rate—
Protocol—
Firmware—
RX Bytes0
TX Bytes0
SERIAL MONITOR
Serial output will appear here when a device is connected...
Compatible Devices:
USB OscilloscopeArduinoESP32STM32RP2040
Logic AnalyzerSCPI InstrumentsBus Pirate
Requires Chrome/Edge 89+ with WebSerial
PROBE COMPENSATION — 1kHz SQUARE WAVE
Undercompensated
Compensated ✓
Overcompensated
CALIBRATION PROCEDURES
① Probe Compensation
Connect 10× probe to CAL output (1kHz square wave). Adjust trimmer until square wave edges are sharp with no overshoot or rounding. The canvas shows the effect of your compensation capacitor adjustment.
Status
Properly Compensated
② DC Offset Zero
Short probe tip to ground clip. Adjust vertical position until trace sits exactly on the center graticule line. This zeroes the DC offset.
CH1 Offset
0.00 mV
③ Gain Calibration
Apply known voltage (e.g., 1.000V reference). Adjust gain trim until measurement matches reference. Verify across all V/div settings.
Gain Error
±0.00%
④ Timebase Calibration
Apply known frequency source. Verify cursor measurements match expected period/frequency. Timebase accuracy should be within ±50ppm.
Timebase Error
±0 ppm
FPGA IDE
VHDL · REAL LOGIC EVALUATION · SYNTHESIS · WAVEFORM
WAVEFORM — LOGIC EVALUATOR
Click ▶ Simulate
Ready for synthesis...
RPi Terminal
SIMULATED LINUX · GPIO · I2C · SPI · PYTHON
pi@rpi5 — bash
SSH Connected
ELEC//LAB RPi Terminal Emulator v3.0 — Phase 1
Simulated Raspberry Pi 5 — ARM Cortex-A76 · 8GB · Bookworm
GPIO: 40-pin header · I2C: bus 1 @ 0x48,0x68,0x77 · SPI: CE0
Type 'help' for available commands
pi@rpi5:~ $
GPIO Header — 40 Pin
I2C Bus Scan
Protocol Analyzer
I2C · SPI · UART · REAL-TIME DECODE
| Time | Type | Hex | Bin | Interpretation |
|---|
Op-Amp Laboratory
7 TOPOLOGIES · GAIN · BANDWIDTH · FREQUENCY RESPONSE
Ω
Ω
nF
Vpp
V
V
Closed-Loop Gain
—
Gain (dB)
—
Bandwidth (-3dB)
—
Vout
—
Rin
—
Transistor Laboratory
BJT BIASING · MOSFET SWITCHING · LOAD LINES · I-V CURVES
V
Ω
Ω
Ω
V
Ic (Collector)
—
Ib (Base)
—
Vce
—
Power
—
Region
—
ADC / DAC Deep Dive
SAMPLING · NYQUIST · QUANTIZATION · ALIASING · RECONSTRUCTION
1000 Hz
8000 Hz
Nyquist Freq
—
fs / fsig
—
SNR (ideal)
—
Quant. Step
—
Aliasing?
—
Power Electronics
BUCK · BOOST · BUCK-BOOST · LDO · EFFICIENCY · THERMAL
V
V
A
kHz
mV
Duty Cycle
—
Inductor
—
Output Cap
—
Efficiency
—
Power Loss
—
ΔIL (ripple)
—
PCB Layout Fundamentals
COMPONENT PLACEMENT · TRACE ROUTING · DRC · LAYER STACKUP
Learning Paths
4 TRACKS · THEORY → LAB → QUIZ · SKILL TREE · PROGRESS TRACKING
0
COMPLETED
0
IN PROGRESS
0
XP EARNED
0
DAY STREAK
LEARNING TRACKS
SELECT A TRACK
📚
Select a learning track to begin
Each track progresses: Theory → Interactive Demo → Lab Exercise → Knowledge Check
SKILL TREE
Challenge Mode
BUILD-TO-SPEC · FAULT DIAGNOSIS · QUIZ ENGINE · AUTO-GRADE
Click ▶ Start to begin a quiz challenge.
Lab Notebook
DOCUMENT · MARKDOWN · EXPORT · LAB REPORTS
ENTRIES
PAPER//DESIGN
BLOCK DIAGRAM → VHDL · XDC · TCL · AUTO-WIRE · RESOURCE ESTIMATION
VHDL
XDC
TCL
Monte Carlo Analysis
TOLERANCE SWEEP · TEMPERATURE · NOISE · PARAMETRIC OPTIMIZER
ANALYSIS TYPE
5%
to
STATISTICS
Mean
—
Std Dev (σ)
—
Min
—
Max
—
Yield
—
Cpk
—
HISTOGRAM
Ready
RF & Signal Integrity
SMITH CHART · EYE DIAGRAM · FILTER DESIGN · TRANSMISSION LINES
50
0
Γ (mag)
—
Γ (angle)
—
VSWR
—
Return Loss
—
Mismatch Loss
—
Zin
—
Visualization Engine
BODE PLOTS · NYQUIST · POLAR · WAVEFORM MATH · HISTOGRAMS
0.71
0
-3dB Freq
—
DC Gain
—
Phase Margin
—
Gain Margin
—
Settings
PREFERENCES · SHORTCUTS · DATA MANAGEMENT · PERSISTENCE
GENERAL PREFERENCES
Dark Theme
PCB-dark theme (default)
Scanline Effect
CRT scanline overlay on background
PCB Grid Background
Grid pattern behind content
Animations
Page transitions and pulse effects
Toast Notifications
Status messages for actions
Status Bar Clock
Show time in top bar
SIMULATION PREFERENCES
DATA MANAGEMENT
LocalStorage Used—
Saved Circuits—
Notebook Entries—
Quiz Best Score—
Learning Progress—
KEYBOARD SHORTCUTS
Show all shortcuts?
Quick search
CtrlK
Save state
CtrlS
Navigate (1-5)
Alt1-5
Press ? anywhere to view full shortcut reference overlay
SHARE & EXPORT
ELEC//LAB v3.0 — Phase 5
Kulprit Studios LLC · Full-Stack Electronics Laboratory
17 Engines15 PagesBuild 2026.02
Platform Bridges
SEC//LAB · MATH//LAB · CROSS-PLATFORM
// Kulprit Studios Lab Ecosystem
MATH//LAB
→
ELEC//LAB
→
SEC//LAB
→
CYBER WX
→
KRUCIBLE
Hardware Fault Injection
ELEC + SEC//LAB
Design glitch circuits in ELEC//LAB, use as attack vectors in SEC//LAB. Voltage glitching, clock manipulation, EM fault injection.
DSP Filter Pipeline
MATH + ELEC//LAB
Design filters in MATH//LAB, export coefficients, implement as VHDL in FPGA IDE, verify frequency response with virtual scope.
Side-Channel Analysis
ELEC + SEC//LAB
Measure power traces from FPGA crypto, correlate with statistical tools. CPA/DPA from hardware to key recovery.